1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using scatterometry measurements to control photoresist etch process, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, integrated circuit devices are comprised of hundreds or millions of transistors formed above a semiconducting substrate. By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate 11.
One illustrative process flow for forming the gate electrode 14 will now be described. As shown in FIG. 2, a process layer 17 comprised of a gate insulation material, e.g., silicon dioxide, is formed above the semiconducting substrate 11. Typically, this is accomplished by an oxidation process. Then, a process layer 19 comprised of a gate electrode material is formed above the process layer 17. Typically, the process layer 19 is comprised of polysilicon, and it may be formed by a variety of processes, e.g., by a chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) process. If desired, an anti-reflective coating layer (not shown) may also be formed above the process layer 19 to reduce reflections during subsequent photolithography exposure processes. The anti-reflective coating layer may be comprised of a variety of materials, e.g., silicon nitride, silicon oxynitride, etc. Also depicted in FIG. 2 is a photoresist feature 21. The photoresist feature 21 is part of a patterned layer (not shown) of photoresist material (positive or negative) formed above the process layer 19 using known photolithography techniques. Millions of such photoresist features 21 are formed in a patterned layer of photoresist.
After the photoresist feature 21 is formed, one or more etching processes will be performed to form a gate electrode structure 14 from the underlying process layer 19. In one process flow, prior to etching the process layer 19, the photoresist feature 21 will be subjected to a photoresist etch or trim process to initially reduce the size of the photoresist feature 21 to the size indicated by dashed lines 23. This results in a reduced size photoresist feature 21A. This photoresist trimming process may be accomplished by a variety of techniques. For example, oxygen (O2) may be introduced into the etch chamber to reduce the size of the original photoresist feature 21 to that depicted for the reduced size photoresist feature 21A.
The reduced size photoresist features 21A has a critical dimension 24 that is less than that of the initially formed photoresist feature 21. Through use of this photoresist trim technique, the critical dimension of photoresist features may be reduced to a size smaller than that which may be directly patterned in a layer of photoresist using known photolithography tools. For example, using current photolithography tools and techniques, feature sizes on the order of 0.18 xcexcm may be formed. Of course, efforts are continually being made to improve photolithography tools such that smaller and smaller feature sizes may be formed. Nevertheless, as will be understood after a complete reading of the present application, the present invention may be employed as the performance of photolithography equipment continues to improve.
After the photoresist trim process is performed, one or more etching processes are performed to etch the desired feature in the underlying process layer, e.g., a gate electrode 14 in the process layer 19. For example, an initial anisotropic etching process may be performed to etch through approximately 75% of the process layer 19. Thereafter, an isotropic etching process may be performed on the remaining portion of the process layer 19 to insure the integrity of the underlying process layer 17. The gate electrode structure (not shown) formed using this technique would have sidewalls defined by the dashed lines 25.
One problem encountered with the present photoresist trim process is that there is no direct control employed in determining when to stop the photoresist trim process. That is, typically the photoresist trim process is performed, and gate electrode structures 14 are formed in the underlying process layer 19. Thereafter, the critical dimensions of one or more of the resulting gate electrode structures 14 is measured. If the measured gate electrode structures 14 have a critical dimension greater than a target value, then the duration of the photoresist trimming process is increased for subsequently processed wafers. Conversely, if the measured gate electrodes 14 have a critical dimension less than a target value, then the duration of the photoresist process is decreased on subsequently processed wafers. While such control techniques tend to work, a more direct method of controlling the photoresist trim process is desired.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of using scatterometry measurements to control the photoresist etch process, and a system for accomplishing same. In one embodiment, the method comprises forming at least one grating structure in a layer of photoresist material, the grating structure being comprised of a plurality of photoresist features of a first size, and performing an etching process on the photoresist features of the grating structure to reduce the photoresist features to a second size that is less than the first size. The method further comprises illuminating the grating structure, measuring light reflected off of the grating structure after the etching process is started to generate an optical characteristic trace for the grating structure, comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a grating structure comprised of a plurality of photoresist features having a desired profile, and stopping the etching process based upon the comparison of the generated trace and the target trace.
In another illustrative embodiment, the method comprises forming a process layer above a semiconducting substrate, forming a layer of photoresist material above the process layer, and forming a plurality of photoresist features in the layer of photoresist material, a first group of the photoresist features comprising at least one grating structure, the photoresist features being of a first size. The method further comprises performing an etching process on the plurality of photoresist features to reduce the photoresist features to a second size, the second size being less than the first size, illuminating the grating structure, measuring light reflected off of the grating structure after the etching process is started to generate an optical characteristic trace for the grating structure, comparing the generated optical characteristic trace to a target optical characteristic trace that corresponds to a grating structure comprised of a plurality of photoresist features having a desired profile, and stopping the etching process based upon the comparison of the generated trace and the target trace.